1. Technical Field
The present invention relates to a delay locked loop. More particularly, the present invention relates to a delay apparatus for a delay locked loop that compensates for time required when a clock output by a delay locked loop reaches a data output terminal of a semiconductor memory apparatus.
2. Related Art
In general, a delay locked loop (DLL) synchronizes a phase of an external clock CLK supplied from the outside of a semiconductor memory apparatus and a phase of an internal clock iclk used inside the semiconductor memory apparatus.
The phase of the external clock CLK and the phase of the internal clock iclk are synchronized with each other by the following method. The delay locked loop buffers the external clock CLK and generates the internal clock iclk. The delay locked loop allows the internal clock iclk to pass through a delay apparatus that constitutes a predetermined signal processing time. The delay locked loop allows the internal clock iclk having passed through the delay apparatus to be fed back so as to synchronize the internal clock iclk with the external clock CLK. At this time, the delay locked loop repeatedly performs the above-described process. When the internal clock iclk is synchronized with the external clock CLK, the delay locked loop outputs delay locked loop clocks fclk and rclk.
The delay locked loop clock fclk is synchronized with a falling edge of the external clock CLK, and the delay locked loop clock rclk is synchronized with a rising edge of the external clock CLK.
A general delay apparatus includes an inverter chain or resistors and capacitors that are alternately or repeatedly disposed. A delay apparatus according to the related art for the delay locked loop includes modeling delay devices that are formed by modeling signal processing structures through which a delay locked loop clock reaches an output terminal of a semiconductor memory apparatus from an output terminal of the delay locked loop. The modeling delay devices may be provided at the ends of the delay locked loop.
That is, the delay apparatus for the delay locked loop according to the related art constitutes various signal processing structures through which the delay locked loop clock reaches the output terminal of the semiconductor memory apparatus from the output terminal of the delay locked loop.
For example, in the case of the modeling delay device that models a buffer, the modeling delay device is constructed similarly to the buffer. The modeling delay device has an unchangeable delay time.
The number of modeling delay devices may be changed according to the number of signal processing structures through which the delay locked loop clock reaches the output terminal of the semiconductor memory apparatus from the output terminal of the delay locked loop.
As such, the reason the number of modeling delay devices is determined according to the number of signal processing structures is to delay the delay locked loop clock by an actual signal processing delay time.
During the operation of the semiconductor memory apparatus that uses the delay locked loop, the supplied operation voltage may be changed.
As described above, the delay apparatus for the delay locked loop according to the related art delays and outputs the input signal by the locked delay time regardless of the change in the operation voltage.
However, in accordance with the change in the operation voltage, the delay apparatus for the delay locked loop according to the related art needs to output the phase locked loop clock in a state where the phase of the phase locked loop clock is shifted to the right side or the left side as compared with a normal phase. In this case, the phase difference departs from a predetermined range due to the phase shift, which causes an erroneous operation in the semiconductor memory apparatus.